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Another invalid opcode representation
After the release of radare 1.0 somebody noted a bug in the disassembler, so we made some investigation and saw that udis86 is representing the 83 e4 f0 as "and esp,0xf0" and other disassemblers (olly, gnu objdump, ..) are representing it as: "and esp, 0xfffffff0" The problem is not directly related to udis86, because it is a missrepresentation of what intel really does at low level with this instruction. In the specs says that the 83 opcode should affect only the lowest byte of the register pointed by the second byte. If this operation is performed against EAX we can properly represent the instruction as "AND AL, 0xF0", but neither EBP or ESP has partial access representations. The funny thing is that without having access to a part of a register following the intel syntax the cpu is able to do it, so I understand that this is a bug in the representation for all the disassemblers. Both ones are correct to me because they will act in the same way (maybe the olly,objdump) is more correct, but it does not matches the reality of the instruction. Comments
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